CMOS SRAM Circuit Design and Parametric Test

in Nano-Scaled Technologies

FRONTIERS IN ELECTRONIC TESTING

Consulting Editor

Vishwani D. Agrawal

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Testing Static Random Access Memories

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Andrei Pavlov · Manoj Sachdev

CMOS SRAM Circuit Design

and Parametric Test

in Nano-Scaled

Technologies

Process-Aware SRAM Design and Test

ABC

Andrei Pavlov

Intel Corporation

2501 NW 229th Street

Hillsboro, OR 97124

Series Editor

Vishwani Agrawal

Department of Electrical and Computer

Engineering

Auburn University

Auburn, AL 36849

USA

Manoj Sachdev

University of Waterloo

Dept. Electrical & Computer

Engineering

200 University Ave.

Waterloo ON N2L 3G1

Canada

ISBN 978-1-4020-8362-4 e-ISBN 978-1-4020-8363-1

Library of Congress Control Number: 2008924192

° 2008 Springer Science + Business Media B.V.

No part of this work may be reproduced, stored in a retrieval system, or transmitted in any form or by

any means, electronic, mechanical, photocopying, microﬁlming, recording or otherwise, without written

permission from the Publisher, with the exception of any material supplied speciﬁcally for the purpose of

being entered and executed on a computer system, for exclusive use by the purchaser of the work.

Printed on acid-free paper

9 8 7 6 5 4 3 2 1

springer.com

To Natasha and Daniel

To Sunanda, Aniruddh and Arushi

Foreword

Embedded SRAMs now dominate CMOS computing chips taking well over half of

the total transistor count of high performance ICs. This dominance forces designers

to minimize the SRAM layout area imposing a tight transistor density. This transis-

tor circuit density presents two challenges for the test. The ﬁrst is that virtually all

areas of the cells are active and sensitive to particle-related defects. Secondly, par-

asitic coupling between cells is a major concern. This book addresses both of these

problems.

The strongest approach to test method development examines the failure mecha-

nism under test down to the transistor, interconnect and dielectric level. Test detec-

tion methods are guided by the electronic properties of the failure mechanism. This

analysis style and subsequent development of a test method is called defect-based

testing (DBT). This book is a strong example of the DBT thinking. The authors de-

scribe an comprehensive SRAM test that is supported by abundant simulation and

silicon data. High-density embedded SRAMs require this detailed level of study

to understand how to avoid the severe implications of test escapes in this critical

majority region of modern ICs.

The authors also supply excellent tutorial descriptions of topics that support

SRAMs. This includes design of the memory system and its components, SRAM

cell stability, traditional fault models and test practices, I

DDQ

testing, burn-in chal-

lenges and a particularly relevant Chapter 6 on soft error impact on nano-scaled

SRAM cells. This book is well written and the reader is the beneﬁciary of the large

amount of work by the authors. The book should be read and on the shelf of engi-

neers who deal with high-performance chips.

Professor Chuck Hawkins

University of New Mexico

vii

Preface

The process technology scaling and push for better performance enabled embedding

of millions of Static Random Access Memories (SRAM) cells into contemporary

ICs. In several applications, the embedded SRAMs can occupy the majority of the

chip area and contain hundreds of millions of transistors. As the process technol-

ogy continues to scale deeper into the nanometer region, the stability of embedded

SRAM cells is a growing concern. As a consequence, large SRAM arrays impact all

aspects of chip design and manufacturing because they became the yield-limiters in

modern high-performance ICs. However, the robust detection of SRAM cells with

marginal stability is a non-trivial task. While the traditional march tests are unable

to detect unstable cells, the conventional data retention tests that are intended to ex-

pose marginal cells have unacceptable sensitivity and are uneconomical due to the

long test time and high-temperature requirements. These factors show the growing

disparity between the traditional SRAM test practices and the need for an econom-

ical SRAM cell stability tests that can help to achieve lower defect counts in the

shipped parts. While various aspects of SRAM design and test have been addressed

in special literature, no cohesive text provides a systematic overview of SRAM cell

stability and the specialized design and test approaches it requires.

Therefore, the primary objective of this book is to bridge the gap between the

challenges that the technology scaling brings on SRAM circuit design and the design

and test solutions spanning across the process technology, circuit and system design

and the testing. The book gives an overview of SRAM design and the traditional

SRAM testing. It builds the reader’s understanding on the detailed treatment of the

aspects of SRAM cell stability and the state-of-the-art specialized stability testing

techniques including the test techniques developed by the authors. In addition, since

the unstable SRAM cells are more prone to soft errors, we included an overview

of the sources, mechanisms and the mitigation techniques for soft errors in SRAM

arrays.

The intended audience of this book is graduate students, engineers and profes-

sionals interested in developing understanding and intuition of the challenges faced

by modern SRAM design and test engineers.

x Preface

Authors would like to thank Jose Pineda de Gyvez and Mohamed Azimane

(Philips Research Labs) and Patrick van de Steeg (Philips Semiconductors) for sev-

eral fruitful technical discussions and research cooperation. We appreciate Canadian

Microelectronics Corporation (CMC) for providing the chip fabrication services and

are grateful to Rutger van Veen and Bram Kruseman (Philips Research Labs) for the

help with the creation of the test programs and the test chip measurements. Authors

are thankful to Mark de Jongh for facilitating the publishing of this book.

Authors would like to thank their respective families for invaluable support dur-

ing the preparation of this book. Andrei would like to express special thanks to his

wife Natasha for her endless support and encouragement. Manoj would like to ex-

press his appreciation to his wife Sunanda, their son Aniruddh and daughter Arushi

for their understanding and support.

Andrei Pavlov

Manoj Sachdev

Contents

1 Introduction and Motivation .................................... 1

1.1 Motivation ................................................ 1

1.2 SRAMintheComputerMemoryHierarchy .................... 3

1.3 Technology Scaling and SRAM Design and Test . . .............. 4

1.3.1 Moore’sLaw........................................ 5

1.3.2 ObstaclesinSRAMScaling ........................... 6

1.4 SRAM Test Economics. . . . . . ................................ 7

1.5 SRAM Design and Test Tradeoffs ............................. 8

1.5.1 Area and Stability .................................... 9

1.5.2 Quality and Yield . . . . ................................ 9

1.5.3 TestCoverageandTestTime .......................... 10

1.6 Redundancy . . . . ........................................... 11

2 SRAM Circuit Design and Operation ............................. 13

2.1 Introduction . . . . ........................................... 13

2.2 SRAMBlockStructure...................................... 13

2.3 SRAMCellDesign......................................... 15

2.3.1 Four-Transistor (4T) SRAM Cell with Polysilicon

ResistorLoad ....................................... 15

2.3.2 Six-Transistor(6T)CMOSSRAMCell.................. 16

2.3.2.1 ReadOperation.............................. 17

2.3.2.2 WriteOperation ............................. 19

2.3.3 Four-Transistor (4T) Loadless SRAM Cell . .............. 21

2.4 Cell Layout Considerations . . ................................ 22

2.5 Sense Ampliﬁer and Bit Line Precharge-Equalization . . .......... 26

2.6 WriteDriver............................................... 30

2.7 Row Address Decoder and Column MUX . ..................... 31

2.8 Address Transition Detector . . ................................ 33

2.9 Timing Control Schemes . . . . ................................ 34

2.9.1 Delay-LineBasedTimingControl...................... 35

xii Contents

2.9.2 Replica-LoopBasedTimingControl.................... 35

2.9.3 PipelinedTimingControl ............................. 38

2.10 Summary ................................................. 38

3 SRAM Cell Stability: Deﬁnition, Modeling and Testing ............. 39

3.1 Introduction . . . . ........................................... 39

3.2 StaticNoiseMarginofSRAMCells........................... 40

3.3 SNMDeﬁnitions........................................... 41

3.3.1 Inverter V

, V

and V

......................... 41

3.3.2 Noise Margins NM

and NM

with V

and V

Deﬁned as Stable Logic Points . . . . ..................... 42

3.3.3 Noise Margins NM

and NM

with V

and V

Deﬁned as −1SlopePoints............................ 42

3.3.4 SNM as a Side of the Maximum Square Drawn

BetweentheInverterCharacteristics .................... 44

3.4 AnalyticalExpressionsforSNMCalculation.................... 46

3.4.1 Analytical SNM Expression for a 4T SRAM Cell

withPolysiliconResistorLoad......................... 47

3.4.2 Analytical SNM Expression for a 6T SRAM Cell . . . . . . . . . 49

3.4.3 Conclusions from SNM Analytical Expressions ........... 51

3.4.4 Analytical SNM Expression for a Loadless

4TSRAMCell ...................................... 51

3.4.4.1 Alpha-Power Law Model ..................... 51

3.4.4.2 Analytical SNM Expression Derivation . . . . . . . . . . 53

3.4.4.3 Finding V

and V

......................... 53

3.4.4.4 Finding V

and V

.......................... 54

3.4.4.5 SNM Expression for 4T Loadless SRAM Cell . . . . 55

3.4.4.6 Simulation Results vs. the Analytical Expression . . 56

3.5 SRAM Cell Stability Sensitivity Factors . . ..................... 58

3.5.1 SRAM SNM and Process Parameter Variations . .......... 59

3.5.2 SRAM SNM and Non-catastrophic Defects .............. 62

3.5.2.1 SNM vs. Non-catastrophic Breaks and Bridges . . . 62

3.5.3 SRAM SNM and Operating Voltages Variation . .......... 64

3.6 SRAM Cell Stability Fault Model ............................. 68

3.7 SRAM Cell Stability Detection Concept . . ..................... 69

3.8 March Tests and Stability Fault Detection in SRAMs . . . .......... 72

3.8.1 March11N ......................................... 72

3.8.2 HammerTest........................................ 73

3.8.3 CouplingFaultDetection.............................. 74

3.9 Summary ................................................. 77

4 Traditional SRAM Fault Models and Test Practices ................ 79

4.1 Introduction . . . . ........................................... 79

4.2 Traditional Fault Models . . . . ................................ 80

4.3 Traditional SRAM Test Practices . ............................ 85